Aspects are related generally to computer-based communication systems, and more specifically to processing of inbound back-to-back completions in a communication system of a computer system.
Peripheral component interconnect express (PCIe) is a component level interconnect standard that defines a bi-directional communication protocol for transactions between input/output (I/O) adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission on a PCIe bus. Packets originating at I/O adapters and ending at host systems are referred to as upbound packets. Packets originating at host systems and terminating at I/O adapters are referred to as downbound packets. PCIe transactions include a request packet and, if required, a completion packet (also referred to herein as a “response packet”) in the opposite direction. The PCIe topology is based on point-to-point unidirectional links that are paired (e.g., one upbound link, one downbound link) to form the PCIe bus.
A high-bandwidth PCIe link (x16) can transmit two full transaction layer packets (TLPs) in a single scaled clock cycle and must process two partial completion TLPs simultaneously. PCIe completions can be fragmented into multiple partial completions (also referred to as “completion fragments”) by the completer. Partial completions are issued in address order and must be reassembled by the receiver. After each completion is received, the PCIe completion table (PCT) of the receiver must be updated with a new offset and byte count modified (BCM) values, which are used to look for, error check, and properly process future inbound completions.
In some PCIe instances, the bandwidth is high enough to cause two full PCIe TLPs to be received in a single cycle. TLPs must be processed simultaneously, passing error checks and assembling completion data in the proper location. Due to cycle timing requirements, not all lookup operations, calculations and compares can be done in a single clock cycle, so the processing pipeline is multiple cycles deep. This creates difficulties when two separate pipelines can process pieces of the same completion.